FIELD0_DONE_IE=FIELD0_DONE_IE_0, RGB888A_FORMAT_SEL=RGB888A_FORMAT_SEL_0, LAST_DMA_REQ_SEL=LAST_DMA_REQ_SEL_0, DMA_FIELD1_DONE_IE=DMA_FIELD1_DONE_IE_0, MASK_OPTION=MASK_OPTION_0, BASEADDR_SWITCH_SEL=BASEADDR_SWITCH_SEL_0, DEINTERLACE_EN=DEINTERLACE_EN_0
CSI Control Register 18
| DEINTERLACE_EN | This bit is used to select the output method When input is standard CCIR656 video. 0 (DEINTERLACE_EN_0): Deinterlace disabled 1 (DEINTERLACE_EN_1): Deinterlace enabled |
| PARALLEL24_EN | When input is parallel rgb888/yuv444 24bit, this bit can be enabled. |
| BASEADDR_SWITCH_EN | When this bit is enabled, CSI DMA will switch the base address according to BASEADDR_SWITCH_SEL rather than atomically by DMA completed |
| BASEADDR_SWITCH_SEL | CSI 2 base addresses switching method. When using this bit, BASEADDR_SWITCH_EN is 1. 0 (BASEADDR_SWITCH_SEL_0): Switching base address at the edge of the vsync 1 (BASEADDR_SWITCH_SEL_1): Switching base address at the edge of the first data of each frame |
| FIELD0_DONE_IE | In interlace mode, fileld 0 means interrupt enabled. 0 (FIELD0_DONE_IE_0): Interrupt disabled 1 (FIELD0_DONE_IE_1): Interrupt enabled |
| DMA_FIELD1_DONE_IE | When in interlace mode, field 1 done interrupt enable. 0 (DMA_FIELD1_DONE_IE_0): Interrupt disabled 1 (DMA_FIELD1_DONE_IE_1): Interrupt enabled |
| LAST_DMA_REQ_SEL | Choosing the last DMA request condition. 0 (LAST_DMA_REQ_SEL_0): fifo_full_level 1 (LAST_DMA_REQ_SEL_1): hburst_length |
| BASEADDR_CHANGE_ERROR_IE | Base address change error interrupt enable signal. |
| RGB888A_FORMAT_SEL | Output is 32-bit format. 0 (RGB888A_FORMAT_SEL_0): {8’h0, data[23:0]} 1 (RGB888A_FORMAT_SEL_1): {data[23:0], 8’h0} |
| AHB_HPROT | Hprot value in AHB bus protocol. |
| MASK_OPTION | These bits used to choose the method to mask the CSI input. 0 (MASK_OPTION_0): Writing to memory from first completely frame, when using this option, the CSI_ENABLE should be 1. 1 (MASK_OPTION_1): Writing to memory when CSI_ENABLE is 1. 2 (MASK_OPTION_2): Writing to memory from second completely frame, when using this option, the CSI_ENABLE should be 1. 3 (MASK_OPTION_3): Writing to memory when data comes in, not matter the CSI_ENABLE is 1 or 0. |
| CSI_ENABLE | CSI global enable signal |